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[Other resource] FSM_writing

Description: VHDL/Verilog FSM的优化写法
Platform: | Size: 927 | Author: pc repair | Hits:

[Other] FSM_DESIGN

Description: 非常好的FSM设计，对于学习VHDL的人有很好的参考价值。-very good design, VHDL for the study of a very good reference value.
Platform: | Size: 571392 | Author: zhangbijun | Hits:

[Other] spi_master

Description: SPI wishbone master and verification environment
Platform: | Size: 2506752 | Author: 王小墨 | Hits:

[VHDL-FPGA-Verilog] fileread

Description: file_read vhdl code provide by my teacher for reading file into FSM-file_read vhdl code
Platform: | Size: 1024 | Author: hongwan | Hits:

[VHDL-FPGA-Verilog] topsequence

Description: modeling of fsm in vhdl
Platform: | Size: 1024 | Author: MILIND | Hits:

[VHDL-FPGA-Verilog] fsm_tb

Description: An odd parity checker as an FSM using VHDL
Platform: | Size: 1024 | Author: Ahmed | Hits:

[VHDL-FPGA-Verilog] johnson_encoding_angle

Description: An FSM using VHDL and Johnson state encoding for states
Platform: | Size: 1024 | Author: Ahmed | Hits:

[VHDL-FPGA-Verilog] USE_FSM_DEDIGN_SRAM

Description: 用FSM（有限状态机）设计SRAM的VHDL语言-With the FSM (finite state machine) design of the VHDL language SRAM
Platform: | Size: 12288 | Author: 高群 | Hits:

[VHDL-FPGA-Verilog] mealy

Description: MEALY fsm source code in vhdl, implemented on fpga
Platform: | Size: 328704 | Author: alyna | Hits:

[VHDL-FPGA-Verilog] moore

Description: MOORE fsm source code in vhdl, implemented on fpga
Platform: | Size: 199680 | Author: alyna | Hits:

[VHDL-FPGA-Verilog] ReadFsm

Description: VHDL小程序，read FSM。可以作为VHDL一次作业使用。包含测试文档testbench。-VHDL applet, read FSM. A job can be used as a VHDL。VHDL code and testbench.
Platform: | Size: 2048 | Author: 雪睿 | Hits:

[VHDL-FPGA-Verilog] AD_fsm

Description: AD7892的状态机VHDL代码。完成时序控制，4通道数据采集和AD转换。-the FSM of AD7892
Platform: | Size: 1024 | Author: 马寅 | Hits:

[VHDL-FPGA-Verilog] AssignmentP7

Description: 1. Design a VHDL model for a 4-bit up-and-down synchronous binary counter with carry and borrow signs using FSM. Verification of this design is especially appreciated.
Platform: | Size: 205824 | Author: 魏攸 | Hits:

[Industry research] 04470136.rar

Description: This paper is focus on to implement IEEE 802.3 XMAC transmitter using different VHDL coding techniques. We propose consequences of VHDL coding styles on area utilization and speed. Optimization for maximum speed can be achieved by FSM based approach. While targeting higher speed device area utilization is severely affected To have a balance among area and speed optimization, we have explored synthesis options along with VHDL coding styles. ,This paper is focus on to implement IEEE 802.3 XMAC transmitter using different VHDL coding techniques. We propose consequences of VHDL coding styles on area utilization and speed. Optimization for maximum speed can be achieved by FSM based approach. While targeting higher speed device area utilization is severely affected To have a balance among area and speed optimization, we have explored synthesis options along with VHDL coding styles.
Platform: | Size: 3558400 | Author: Mohd Elsoufi | Hits:

[Algorithm] hdlsrc

Description: In mathematics, the greatest common divisor (gcd), also known as the greatest common factor (gcf), or highest common factor (hcf), of two or more integers(at least one of which is not zero), is the largest positive integer that divides the numbers without a remainder. For example, the GCD of 8 and 12 is 4. here GCD algorithm of int16 bit is implemented in vhdl. This has module like fsm(finite state machine),datapath which are used to compute greatest common divisor of two numbers.
Platform: | Size: 5120 | Author: nilesh | Hits:

[VHDL-FPGA-Verilog] seg

Description: 可以很好学习的学习状态机！学习逻辑能力,提高自己的代码书写能力！-FSM study,if you like study vhdl,you could download this zip to study
Platform: | Size: 1558528 | Author: 王辉 | Hits:

[Other] State-Machine-Verilog

Description: State Machine Design Techniques for Verilog and VHDL.pdf -Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
Platform: | Size: 251904 | Author: chenwei | Hits:

[VHDL-FPGA-Verilog] swfsm

Description: stopwatch的FSM状态机的代码，可供初学者学习参考如何编写状态机-the finite state machine vhdl code for the simple stopwatch file
Platform: | Size: 2048 | Author: Echo Li | Hits:

[Other] lab03-.tar

Description: vhdl about 3 stage control block of cpu-vhdl control block of the 3 stage cpu(FSM)
Platform: | Size: 288768 | Author: anna | Hits:

[VHDL-FPGA-Verilog] controller

Description: Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang Controller (control logic plus state register) VHDL FSM modeling- Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang Controller (control logic plus state register) VHDL FSM modeling
Platform: | Size: 2048 | Author: mohamed | Hits:
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